Realisation of a modified CMAC architecture using reconfigurable logic devices

<p>The CMAC is a perception-like computational structure proposed originally by J. Albus in 1975. It is attractive for real-time applications, as it can be realised using conventional RAM, and the output computation involves the summation of a fixed (usually small) number of weights. The selection of weights is carried out by means of hash coding, which unfortunately introduces hashing collisions. A modification of the original architecture is proposed, which allows the elimination of intravector collisions arising when two or more variables of the same address vector (induced by a given input vector) map onto the same memory position. The improved method is based on a blocked rather than a continuous weight memory scheme. A project has been undertaken to find and efficient hardware implementation of the CMAC structure using programmable hardware (EPDLs and FPGAs) as building blocks. The CMAC has been realised as a single Xillnx FPGA device. The chip has been incorporated into an AT computer card to be used as a high speed hardware accelerator in CMAC applications.</p>